Modulators and demodulators which modulate a carrier oscillation and received data on the basis of standardized modulation and demodulation methods depending on the data to be transmitted, and which demodulate received data in a corresponding manner, are used within transmitting and receiving devices in mobile radios. Known modulation and demodulation methods include, for example, GSM (Global System for Mobile Communication), EDGE (Enhanced Data Rate for GSM Evolution), TIA-EIA 136 (Telecommunication Industry Associations/Electronic Industry Association), UTRA FDD (UMTS-Terrestrial Radio Access Frequency Division Duplex), UTRA TDD (UMTS-Terrestrial Radio Access Time Division Duplex), and IS-95. In general, the modulators and demodulators comprise two or more functional units, for example a baseband module (which produces a signal which complies with a standard, generally a complex-value signal) from the data to be transmitted with the aid of digital signal processing, and a radio-frequency module, which shifts this complex-value signal to a radio frequency and transmits it as a real-value signal with suitable amplification via an antenna. The received payload data is demodulated in a corresponding manner by the radio-frequency module to form a complex-value signal, and the received, demodulated data is processed further in a baseband module.
Different physical requirements for the baseband and radio control frequency module result in these functional units of the vehicle being formed in separate integrated circuits, using different manufacturing technologies. In the transmission direction, the modulating baseband signal must be transmitted in a suitable form to the radio-frequency module. In the receiving direction, the demodulating radio-frequency signal must be transmitted to the baseband module in a suitable form. In this case, a suitable interface may be provided between the baseband module and the radio-frequency module, and may be in the form of an analogue signal interface. In this case, the baseband signals are normally produced at this analogue interface in the form of complex-value baseband signals, which are broken down into a real part and an imaginary part as a so-called I/Q signal with an in-phase component and a quadrature component, which is shifted through 90° with respect to it. The I and Q components are introduced generally in each case transmitted as a difference signal, so that two lines must in turn be provided in each case for the transmission of each of the components.
Furthermore, the German Patent Application with the file reference 103 01 303.2, which represents a prior art in accordance with § 3 Clause 2 Patent Act, describes a transmitting/receiving arrangement for mobile radio use, in which the interface between the baseband module and the radio-frequency module is in a completely digital form. However, relatively high data rates occur for data transmission in a digital interface such as this. Bit clock frequencies of 26 MHz are used for data transmission in this case.
In the case of bidirectional data transmission, in which only a single data line is used alternately for both transmission directions between the baseband module and the radio-frequency module, and, furthermore, a single bit clock as well as a single word clock are used, the bit clock line and the word clock line being operated in only one fixed, predetermined direction, a distinction must be drawn to it in two cases. The first case is characterised in that the data line as well as the bit clock line and the word clock line are operated in the same transmission direction. The second case is characterized in that the data line is operated in the opposite transmission direction to the bit clock line and to the word clock line.
If the physical signal delay times are considered, then there is a significant difference between the two situations that have been mentioned. The physical signal delay times are governed essentially firstly by the lengths of the signal lines between the baseband module and the radio-frequency module and secondly by the so-called “pad” delay times. The “pad” delay times are time delays which occur in the signal being transmitted from the chip interior via the electrical “bonding” connection, via the substrate of the housing and the pin connection of the housing, as well as connections to the conductor tracks of a board on which the chip is mounted. This applies in an analogous manner to the signal delay times where the signal is transmitted from the outside into the chip interior.
In order to make it possible to ensure high-speed data transmission, it is necessary for no delay time differences to occur between the data signals, the bit clock signals and the word clock signals. The greater the delay time difference between the signals, and/or the greater the shift between the flanks of a data signal and the flanks of a bit clock signal and/or a word clock signal, the lower is the probability that the data can be sampled and received correctly at the reception end. This problem of delay time difference limits the transmission rate because the greater the delay time differences which occur the less data can be transmitted per unit time.
If the cases mentioned above are considered in terms of the transmission direction of the signals, then, in the first case, all the signal connections are aligned in the same direction. All the transmitted signals are in this case essentially subject to the same delay times or different delay times of the signals are in this case in general caused only by manufacturing tolerances or minor line length differences. Thus, in this case, the relative position of the flanks of the data signals and of the clock signals remains essentially unchanged, thus resulting in data transmission at relatively high speed.
In the second case, in contrast, in which the signals for the bit clock and the word clock are transmitted in the opposite direction to the data, not only the manufacturing tolerances and the line lengths but also the PAD delay times for the introduction of the chip and the extraction of the signal out of the chip must be taken into account for the delay time differences. The total of all the delay time differences which occur when data signals and bit clock as well as word clock signals are transmitted in opposite directions is given by a so-called delay loop. The delay loop can be defined, for example, for a case in which the clock signals are transmitted from the radio-frequency module to the baseband module and the baseband module transmits the data to the radio-frequency module in time with the received clock signals, as follows: first of all, a clock signal is produced by the radio-frequency module. This clock signal is passed out of the radio-frequency module, thus resulting in the generation of a first delay time difference (T1) as a contribution to the delay loop. The transmission of this clock signal via a signal line to the baseband module results in a second delay time difference (T2), which is caused by the line lengths. The insertion of the clock signal from the signal line into the baseband module once again generates a delay time difference (T1). The data is then produced in synchronism with the received clock signal in the baseband module. The process of passing the data signal out of the baseband module results in a further delay time difference (T1). In this case as well, a line length of the data signal line results in a delay time difference (T2) for the transmission of the data signal to the radio-frequency module. A further delay time difference (T1) once again results from the insertion of the data signal into the radio-frequency module, in which the data signal is sampled and received. Thus, in addition to the manufacturing tolerances, this delay loop includes twice the contribution of a delay time difference (T2) resulting from the line lengths and four times the contribution of a delay time difference (T1) caused by clock and data signals being introduced to and extracted from corresponding modules.
Analogously to this, it is also possible to describe a delay loop for the case in which the clock signals are produced by the baseband module, and the radio-frequency module transmits the data signals to the baseband module.
When delay loops such as these occur, undisturbed reception of the data is in general no longer ensured if the delay time in the delay loop is in the same order of magnitude as half a clock period which is used for data transmission. Thus, for example, the period of duration for a clock frequency of 26 MHz is 38.5 ns. The time delays (T1) which are caused by the insertion and extraction of the respective signals are approximately 5 ns for the chip and housing technologies that are used in the mobile radio application field. This means that the problem of delay loops becomes a significant phenomenon even at the clock frequency of 26 MHz which is advantageously used for data transmission in the mobile radio field. These delay loops occur to a particular extent in the case of a digital interface on the one hand, if the baseband module receives monitoring data from the radio-frequency module, and on the other hand, if the radio-frequency module receives transmission data from the baseband module.